C++ Systems Engineer · 6.5+ Years of Experience · Immediate Joiner

Gaurav Anand

Noida, India  ·  +91-9289656293  ·  gaurav.anand54@gmail.com

ExperienceProjectsSkillsGitHub ↗Contact

Systems-focused Software Engineer with 6.5+ years of experience in EDA, distributed systems, and performance-oriented development, specializing in modern C++, multithreading, and design patterns, with a strong track record of independently solving complex problems and quickly adapting to new technologies, including exposure to AI-driven workflows.

Professional Experience

Cadence Design Systems
Jun 2022 – Aug 2024

Software Engineer II

  • •Contributed to the event-driven propagation subsystem of Xcelium's multicore engine by refactoring synchronization from coarse-grained locking to fine-grained strategies and introducing atomic fast paths for hot variables, reducing contention and improving throughput under parallel workloads (validated through performance benchmarks).
  • •Replaced custom synchronization barriers with C++20 primitives and optimized contention-sensitive regions, improving scalability and reducing synchronization overhead in multicore simulation workloads.
  • •Led cross-platform migration of the Xcelium simulation codebase (11M+ LOC) from Linux/GCC (C++11) to macOS/Clang (C++17), resolving platform differences across threading models, system calls, memory mapping, and toolchain compatibility.
  • •Debugged intermittent concurrency defects using Undo time-travel debugging and mentored junior engineers on concurrency-aware development practices.
Airtel Africa Digital LabsPayroll: Intellismith
Apr 2025 – Apr 2026

Senior Software Engineer

  • •Partnered with product managers to understand business requirements and deliver end-to-end solutions, including API development, deployment, and production releases.
  • •Developed a supervised learning model using historical transaction, latency, retry, and error logs millions of records to identify patterns associated with delayed or failed operations, enabling earlier detection of potential transaction failure.
Interra Systems
Dec 2021 – May 2022

C++ Developer

  • •Developed a compiler for a memory description language using Flex and Bison, generating an LALR-based parser for configuration validation and input processing.
  • •Implemented AST construction, semantic validation, and structured error handling for the compiler front-end, improving robustness and correctness of configuration parsing.
Texas Instruments
Jan 2019 – Nov 2021

Software Engineer

  • •Supported Design for Testability (DFT) flows for automotive radar SoCs.
  • •Worked on serial interfacing protocols (SPI/UART) for radar systems, contributing to communication and data exchange between hardware components.

Projects

Celeris

Active

C++20 multicore event-driven simulation engine with pluggable synchronization strategies (coarse-grained, fine-grained, atomic). Includes a browser UI with live benchmarks and Verilog hot-path analysis.

C++20MultithreadingSimulationFastAPIPython
GitHub ↗Try Now ↗

MDL Compiler

Active

Compiler front-end for a memory description language using Flex and Bison — LALR parser, AST construction, semantic validation, and structured error handling. Browser walkthrough of each compiler stage.

CFlexBisonCompiler DesignPython
GitHub ↗Try Now ↗

SpecPilot RAG

Active

Grounded assistant for technical manuals and engineering runbooks. Built with lexical retrieval, a PyTorch reranker, and Hugging Face generation to return citation-backed answers over long technical notes.

PyTorchRAGLLMHugging FaceFastAPI
GitHub ↗Try Now ↗

Design Patterns Visual

Active

10 Gang of Four patterns — Observer, Strategy, Command, Visitor, Factory, Builder, Singleton, Decorator, Adapter, Facade — each with an animated structure diagram, C++ implementation, and real-world usage in EDA tools, compilers, and systems software.

C++Next.jsFastAPIDesign PatternsSVG
GitHub ↗Try Now ↗

NeuroPowerRL

Exploring

Learning-based framework for proactively optimizing circuit power before expensive simulation, modeling circuits as graphs and capturing switching behavior over time through a hybrid GNN + temporal architecture. RL-driven closed-loop optimization for node-level gating and activity reduction.

PythonPyTorchGNNReinforcement LearningEDA
GitHub ↗

Core Skills

Languages & Software Engineering

C++Object-Oriented Design (OOD)Design PatternsSOLID PrinciplesData Structures & AlgorithmsCode ReviewUnit TestingDockerGitScrumREST API IntegrationMicroservices

Systems & Concurrency

MultithreadingThread SafetySynchronizationAtomic OperationsLocking StrategiesRace Condition AnalysisMemory Management

Performance & Architecture

Performance OptimizationEvent-Driven ArchitectureScalabilityTail Latency Analysis (p95/p99)Critical Path Analysis

EDA & Hardware Exposure

XceliumDesign for Testability (DFT)Hardware Description Languages (HDL)TestbenchesTclParsing & Compiler Concepts

Debugging & Toolchain

LinuxClang/GCCGDBUndo Time-Travel DebuggingValgrindSanitizersCross-Platform Migration

AI/ML (Exposure)

RAGLLMsHugging Face TransformersGraph Neural NetworkReinforcement LearningPythonPyTorch (basics)

Education

IIT Patna

M.Tech in Artificial Intelligence (Hybrid)

2025 – 2027

Thapar Institute of Engineering & Technology

B.E. in Electronics Engineering · CGPA: 8.05

2015 – 2019